1. Field of the Invention
The present invention relates to electronic circuits and, more specifically, to an electronic delay circuit that maintains a minimum amount of delay irrespective of a power supply voltage applied thereto.
2. Description of the Prior Art
Integrated circuits are powered by a power supply. A power supply provides a voltage to each of the transistors on an integrated circuit, without which the transistors would not be able to operate. The power supplies used in most high end integrated circuits are external to the integrated circuit and the integrated circuit includes a complicated network of conductors that connect the power supply to the individual transistors in the circuit.
Power supply voltage is often determined after integrated circuit processing is complete. Voltage is tuned to optimize power and performance. Increasing voltage reduces circuit delay, thereby increasing performance, but it also increases power usage by the circuit. There are many circuits, such as pulse generators and dynamic circuits, where some delay dependence on voltage is desired, but the circuits lose functionality if certain delays in critical paths are reduced too far. This can cause an otherwise good chip to be discarded because it does not meet power, performance, and functionality specifications.
An existing pulse generator circuit 100 is shown in FIG. 1. This circuit is sometimes referred to as a “clock chopper.” Typically the circuit 100 includes a delay element 112 that employs a series of inverters or other typical delay circuits. The input signal 110, which typically includes a transition such as a low-to-high transition or a high-to-low transition, is delayed through the delay element 112 and the delayed and inverted signal is ANDed 116 with the original input signal to generate an output pulse.
A timing diagram relating the input signal 110, the inverted delay output 116 and the output pulse signal 120 is shown in FIG. 1B. As the power supply voltage (Vdd) applied to the delay element is increased, the amount of time until the corresponding transition is generated at the inverted delay output 116 tends to decrease. This tends to cause width of the pulse at the output 120 to narrow. At some point, as the power supply voltage increases the output pulse width becomes too narrow, at which point the output is not recognized as a pulse by subsequent circuitry, which can cause a malfunction.
As shown in FIG. 1C, shortly after a transition at the input 110 occurs (a low-to-high transition in the example shown), a copy of the transition is generated at the output. After a delay corresponding to the delay in the delay element, an opposite transition occurs at the output (a high-to-low transition in the example shown). If the power supply voltage (Vdd) is relatively low and the corresponding signal voltage is low 110′, the opposite transition might occur as shown in curve 120′ and the resulting pulse would be relatively broad; on the other hand, if the power supply voltage (Vdd) is relatively high and the corresponding signal voltage is high 110″, the opposite transition might occur as shown in curve 120″ and the resulting pulse would be relatively narrow.
Therefore, there is a need for a circuit that allows for some delay dependence on voltage, but that limits such dependence as voltage is increased past a predetermined threshold.